Bounded by design. Verifiable by construction. Testable by default.
We don’t make chips that can be verified. We make chips where verification is finite, exhaustive, and tractable — a 32-bit deterministic GALS-CISC microcontroller built around three bounded architectural domains, each with an explicit testing payoff.
The verification gap. Modern instruction sets sit inside a 2³² address-shaped behaviour cloud. Decoders interact with mode bits, prefix layers, and field-level encoding tricks. The result: ATPG sampling becomes the only practical option, formal equivalence checking falls over past a depth of ~16–20, and coverage gaps live exactly where field interactions are densest. Every modern CPU project knows the shape of this curve. Most of them just absorb the cost.
Testability is a discipline, not a metric. Test engineers don’t want better-marketed silicon; they want finite state spaces, observable signals, and decidable equivalence. ATPG should converge in minutes, not weeks. Formal EC should run RTL ↔ ISA-spec, not just RTL ↔ gate. Post-silicon trace should decode without guessing. These outcomes are properties of architecture, not afterthoughts of DFT — and they cost ten times more when retrofitted.
Finite is the new fast. Detronyx makes three design choices upfront: a bounded 8-bit opcode space, hardware-typed data, and an address-independent constant address space. None of the three is theoretically novel. What is novel is that all three are held simultaneously, and none is allowed to silently grow under implementation pressure. That commitment is the entire product story.
The deeper truth: if your chip’s behaviour cloud is 2³², you are already negotiating with the verification gap. Detronyx negotiates first.
The Detronyx architecture is structured as 3 bounded behavioural domains, each with an explicit testing payoff, plus 5 architectural mechanisms that implement and protect those domains. The architectural extensions are not the headline — the finite domains are. Mechanisms exist to keep the domains finite.
Each domain carries (a) its size, (b) its architectural role, and (c) its AT-tag: the testing payoff the verification team gets for free.
2⁸ = 256 entries
8051-rooted ISA, finite by design. Atomic decode — one opcode = one meaning.
2⁸ = 256
Hardware-typed data. Type information rides with the value, not the address.
2¹⁶
Constant data addressed independently of physical memory layout. Address-independent equivalence: the constant domain is referenced by logical identity, not by physical placement.
The five extensions are not the product story; they are the implementation contract that holds the three domains finite.
The point is not that any one of these choices is novel. The point is that we hold all three domains finite simultaneously, and we let neither implementation pressure nor schedule pressure compromise any of them. That is what we mean by testable by default.
Most chip startups talk verification as an aspiration. Detronyx talks it as a deliverable. Below are the four killer-features your verification team gets when the architecture lands on their desk — written in their language, not ours.
01 · Killer-feature
ISA ↔ RTL formal EC is computationally tractable when the instruction space is bounded. With 256 opcodes and a pure-function length derivation, the decoder is the smallest formal-EC unit in the entire core. ATPG over the decoder reaches 100% structural coverage in minutes, not days.
02 · Killer-feature
Hardware-typed data turns semantic corruption into an observable fault. ECC catches bit-level corruption; TDM catches type-level corruption. The result: a new fault model — type-mismatch — joins stuck-at, transition, and cell-aware in your fault library. Type-check coverage becomes a first-class metric.
03 · Killer-feature
Globally-asynchronous trace nodes are a known nightmare. Detronyx pushes the async crossing to a single sync stage per boundary, with FIFO + VALID protocols you can write down. Result: post-silicon trace timing is deterministic; the JTAG / on-chip trace stream decodes without statistical reconstruction. Metastability MTBF is a calculable number, not a hand-waved one.
04 · Killer-feature
RTL ↔ netlist EC scope does not grow with the memory map. Constant-side regression sets are stable across memory-layout iterations. Cross-layer evidence — ISA ↔ RTL ↔ netlist — composes cleanly.
If your verification cost curve flattens before tapeout instead of after, the architecture earned its keep.
Modern silicon is too complex for any single discipline to lead end-to-end. Architecture, RTL design, firmware, verification, PCB, mechanical, physics, and program management each see only a slice of the truth. Detronyx Open Co-Design is our answer — specialised AI agents, each scoped to a single discipline, collaborating around a single source-of-truth representation under continuous human direction.
The same loop that builds the chip builds its verification evidence. By the time silicon reaches a verification team, the methodology has produced the design-history file, the EC scaffolding, the regression manifest, and the trace-decode reference — as build-outputs, not as documentation tasks.
We intend to publish the methodology as an open specification. Implementation libraries, agent role contracts, and IR schemas will be released in stages alongside the silicon programme.
The methodology is the product, almost as much as the silicon is.
Tapeout dates and partner specifics on the public surface stop here. The NDA brief carries the rest.
Tower Semiconductor is the production foundry; the target node is 130nm-class (final variant subject to design-partner alignment within that class). We commit to the foundry and the node class up front; final node-variant selection is one of the few items that can move slightly between now and tapeout. The architecture is designed to retarget within the 130nm-class envelope.
GF180 carries the first tapeout as a prototype demonstrator. It validates the three finite domains and their mechanisms on an open, auditable PDK class, and gives partners a working dev-board target ahead of production silicon. First signoff anchors to 30.06.2026.
Target initial run (~1000 chips, via MPW / wafer.space). Indicative allocation:
Run size is a planning target tied to the MPW shuttle slot we are aiming for; final wafer count is settled at tapeout. We are signalling intent and capacity here, not contractual delivery.
Embedded NVM is ReRAM-class, XIP-capable. NVM-vendor selection is Detronyx-internal — not in scope of design-partner co-design. Specific vendor named only after signed mutual NDA and licensing terms.
Detronyx is an Israeli verification methodology meeting Israeli silicon production. From bounded architecture to certified part, the entire stack is sovereign-Israeli — design, methodology, production, IP. Full-stack national capability, by construction.
Four verticals where verification cost is the dominant integration cost — and where a chip designed around finite, observable, exhaustively-testable domains pays itself back the fastest.
On-device inference inside a real-time control envelope. Predictable inference latency is a safety property, not a quality-of-service property. Bounded ISA + deterministic GALS = a per-inference timing contract you can certify against.
Cert-track subsystems where every microsecond of unbounded uncertainty becomes a documented mitigation. TDM gives you a hardware-native fault detector beyond ECC; bounded ISA gives you formal-EC evidence; the decoupled constant address space gives you regression stability across silicon revisions.
Israeli IP, Israeli production, Israeli verification methodology — built for procurement contexts where full-stack auditability is a precondition, not a feature. Deterministic timing closes the side-channel surface analytically — a testing advantage, not a security claim.
Auditable design history is the entry ticket. Detronyx ships verification artefacts as build-outputs of the methodology — type-check coverage reports, ISA ↔ RTL EC evidence, predictable post-silicon trace — alongside the part.
If your platform is in one of these markets and your current MCU starts the integration conversation with “almost deterministic”, we should talk.
We are bringing on a small founding cohort of 3–5 design partners — engineering teams who get the first silicon, integration support, and the right to propose target performance parameters during the finalisation phase. The pre-tapeout window is short by design. First signoff is 30.06.2026; the target initial run (~1000 chips, via MPW / wafer.space) carries an indicative ~900-chip allocation for partners and early market.
Influence scales with integration depth. Each design partner self-selects a tier; Detronyx confirms fit during onboarding.
| Tier | Integration depth | Benefits |
|---|---|---|
| Tier 1: Light | Off-the-shelf MCU + standard board | Early dev-board access · integration support · technical Q&A access to the engineering team |
| Tier 2: Medium | Custom firmware + peripheral configuration | All Tier 1, plus: integration preferences (priority in roadmap) · dedicated engineering touch · right to propose target performance parameters |
| Tier 3: Deep | Co-design at peripheral / SoC integration level | All Tier 2, plus: extended NRE engineering support · deeper architecture-team access during finalisation · priority on next-gen feedback |
Shared baseline across all three tiers. Every design partner — Tier 1, 2, or 3 — receives a dev-board cut from the 30.06.2026 first signoff (target initial run ~1000 chips, via MPW / wafer.space; ~900 indicative partner+market allocation). The baseline is the same; the depth of co-engagement is what tier’ing changes.
Four areas are not subject to design-partner influence at any tier. These are Detronyx-internal or architecturally locked:
Email contact@detronyx.com
with subject line Design Partner — [Your Company].
We respond to every qualified inquiry within 5 business days.
Co-Founder & Chief Architect
Multidisciplinary engineer working across hardware, software, and system architecture. Focused on making complex engineering systems understandable and controllable in practice — bridging firmware, RTL, verification, and physical implementation under real constraints. Currently pursuing research in Electrical Engineering on system architecture and the limits of complexity in modern hardware.
CEO
Author of Lean Innovation 3.0. Founder, Maof Startup. Twenty-plus years building deep-tech ventures from earliest stage to operational scale.
A wider technical and advisory team is in formation. Selected names will be added under their own consent and confirmation.
Three paths in, depending on what you need.
Path 1 · primary
See §9. Apply via the program section above, or write directly to
contact@detronyx.com
with subject line Design Partner — [Your Company].
Path 2 · general
contact@detronyx.com — press, investor (informational), foundry / supply-chain, hiring / collaboration. We triage and route internally.
Path 3 · NDA-gated
Request via
contact@detronyx.com
with subject Technical Brief (NDA). Manual approval. Please
give us a working week and a domain email we can verify.
By contacting Detronyx you agree to be contacted in reply. We do not share contact details with third parties. NDA-gated requests are reviewed individually; an NDA must be executed before any technical material is shared.
It means we choose architectural commitments — bounded ISA, hardware-typed data, an address-independent constant domain — that make verification finite, exhaustive, and tractable as a property of the architecture, not as an emergent outcome of the implementation. Verifiability is the means; testability is the end.
No. We are an 8051-rooted 32-bit ISA family — chosen because the 256-entry opcode space gives us exhaustive ATPG and bounded formal EC out of the box. RISC-V is a fine ISA for many use cases; ours is not one of them.
Embedded NVM is a determinism property as well as a memory property. ReRAM-class technology gives us a predictable boot path, a predictable update window, and an XIP-capable address space we control end-to-end. Vendor selection is Detronyx-internal; specific vendor named only after signed mutual NDA and licensing terms.
Tower Semiconductor, 130nm-class [IP-FENCE OK]. Final variant within the 130nm class is settled in the design-partner alignment phase. The architecture is designed to retarget within the 130nm-class envelope by construction. Process-node selection itself is Detronyx-internal — partner influence sits in peripheral / firmware / integration scope, not in node choice.
First signoff (GF180 prototype demonstrator) is 30.06.2026, with a target initial run (~1000 chips, via MPW / wafer.space) — indicative split ~100 internal / ~900 to partners + early market, settled at tapeout. Design-partner dev-boards ship within ~6 weeks of signoff (Q3 2026). A technical brief is available now under NDA — request via contact@detronyx.com.
We are a deep-tech silicon design company. The product is the chip and the methodology that produces it. We are open to IP-licensing and ASIC-services conversations with the right design partners — see §9.
Israel. The architecture is Israeli, the methodology is Israeli, and production lands at Tower Semiconductor [IP-FENCE OK]. Specific operational detail is shared in the NDA brief.
Not yet — we are pre-tapeout. The methodology is engineered to produce certifiable evidence at every layer, so a downstream certification programme attached to a real customer engagement starts with the design-history file already in hand.
